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Integrated Circuit Systems, Inc.
ICS93718
DDR and SDRAM Buffer
Recommended Application: DDR & SDRAM fanout buffer, for VIA Pro 266, KT266 and P4X266 DDR chipsets Product Description/Features: * * * * * * * * Low skew, fanout buffer 1 to 12 differential clock distribution I2C for functional and output control Feedback pin for input to output synchronization Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2 DDR DIMMs Frequency supports up to 200MHz (DDR400) Supports Power Down Mode for power mananagement CMOS level control signal input
Pin Configuration
FB_OUT VDD3.3_2.5 GND DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 VDD3.3_2.5 GND DDRT2_SDRAM4 DDRC2_SDRAM5 VDD3.3_2.5 BUF_IN GND DDRT3_SDRAM6 DDRC3_SDRAM7 VDD3.3_2.5 GND DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM10 DDRC5_SDRAM11 VDD3.3_2.5 SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL_DDR* VDD2.5 GND DDRT11 DDRC11 DDRT10 DDRC10 VDD2.5 GND DDRT9 DDRC9 VDD2.5 PD#* GND DDRT8 DDRC8 VDD2.5 GND DDRT7 DDRC7 DDRT6 DDRC6 GND SCLK
Switching Characteristics: * OUTPUT - OUTPUT skew: <100ps * Output Rise and Fall Time for DDR outputs: 500ps 700ps * DUTY CYCLE: 47% - 53%
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3
Functionality
MODE DDR Mode DDR/SD Mode PIN 48 VDD 3.3_2.5 2.5V PIN 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21, 22 These outputs will be DDR outputs These outputs will be standard SDRAM outputs
BUF_IN
SEL_DDR=1
SCLK SDATA SEL_DDR* PD#
Control Logic
DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM10 DDRC5_SDRAM11 DDRT(11:6) DDRC (11:6)
SEL_DDR=0
3.3V
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ICS93718
ICS93718
Pin Descriptions
PIN NUMBER 1 2, 8, 12, 17, 23, 3, 9, 14, 18, 26, 31, 35, 40, 46 45, 43, 39, 34, 30, 28, 44, 42, 38, 33, 29, 27, 21, 19, 15, 10, 6, 4 PIN NAME FB_OUT VDD3.3_2.5 GND DDRT (11:6) DDRC (11:6) DDRT (5:0) SDRAM (10, 8, 6, 4, 2, 0) TYPE OUT PWR PWR OUT OUT OUT OUT IN I/O IN PWR DESCRIPTION Feedback output, dedicated for external feedback 2.5V or 3.3V voltage supply to pins 4, 5, 6, 7, 10, 11, 15 , 16, 19 , 20, 21, 22 Ground "Tr ue" Clock of differential pair outputs. "Complementory" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input "Complementory" clocks of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input Single ended buffer input Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input 2.5V voltage supply Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled. The latency of the power down will not be greater t h a n 3 m s. Select input for DDR mode or DDR/SD mode 0=DDR/SD mode 1=DDR mode
DDRC (5:0) 22, 20, 16, 11, 7, 5 SDRAM (11, 9, 7, 5, 3, 1,) 13 24 25 32, 37, 41, 47 BUF_IN SDATA SCLK VDD2.5
36
PD#
IN
48
SEL_DDR
IN
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ICS93718
Byte 6: Output Control (1= enable, 0 = disable)
Byte 7: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 48 45, 44 43, 42 39, 38 34, 33
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SEL_DDR (Read back only) (Reserved) (Reserved) (Reserved) DDRT11, DDRC11 DDRT10, DDRC10 DDRT9, DDRC9 DDRT8, DDRC8
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 30, 29 28, 27 21, 22 19, 20 15, 16 10, 11 6, 7 4, 5
PWD DESCRIPTION 1 DDRT7, DDRC7 1 DDRT6, DDRC6 DDRT5, SDRAM10 1 DDRC5_SDRAM11 DDRT4_SDRAM8 1 DDRC4_SDRAM9 DDRT3_SDRAM6 1 DDRC3_SDRAM7 DDRT2_SDRAM4 1 DDRC2_SDRAM5 DDRT1_SDRAM2 1 DDRC1_SDRAM3 DDRT0_SDRAM1 1 DDRC0_SDRAM0
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ICS93718
Absolute Maximum Ratings
Supply Voltage (VDD & VDD2.5) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND -0.5 V to VDD +0.5 V 0C to +85C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR = 0 SDRAM Outputs VDD = 3.3V, TA = 0 - 85C; (unless otherwise stated)
PARAMETER Input High Current Input Low Current
SYMBOL CONDITIONS IIH VI = VDD or GND IIL VI = VDD or GND IDD3.3_2.5 CL = 0pf, 133MHz CL = 0pf, 133MHz Operating Supply Current IDD2.5 CL = 0pf, all frequencies IDDPD Output High Current IOH VDD = 3.3V, VOUT = 1V IOL VDD = 3.3V, VOUT = 1.2V VDD = 3.3V, VOH = -12mA VDD = 3.3V I OH= 12mA VI
=
MIN -100
TYP 1 -20 200 100 3 -74
MAX 10 250 200 10 -18
UNITS A A mA mA mA mA mA V
Output Low Current
26 2
42 2.95 0.35 2 0.4
High-level output voltage VOH Low-level output voltage Input Capacitance1
1
VOL CIN
GND or VDD
pF
Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=0 SDRAM Outputs VDD=3.3V, TA = 0 - 85C; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP 3.0 3.3 VDD3.3_2.5 Power Supply Voltage VDD2.5 2.3 2.5 SEL_DDR, PD# input 2.0 Input High Voltage VIH Input Low Voltage Input voltage level
1
MAX 3.6 2.7 0.8
UNITS V V V V
VIL VIN
SEL_DDR, PD# input VDD
Guaranteed by design, not 100% tested in production.
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ICS93718
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR = 1 DDR/DDR_SDRAM Outputs VDD=2.5, TA = 0 - 85C; (unless otherwise stated)
PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current Output Low Current High-level output voltage Low-level output voltage Output differential-pair crossing voltage Input Capacitance1
1
SYMBOL IIH IIL IDD2.5 IDDPD IOH IOL VOH VOL VOC CIN
CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf, 133MHz CL = 0pf, all frequencies VDD = 2.5V, VOUT = 1V VDD = 2.5V, VOUT = 1.2V VDD = 2.5V, VOH = -12mA VDD = 2.5V IOH = 12mA
MIN -100
TYP 1 -25 76 3 -74.5 42.5 2.3 0.35
MAX 10 200 10 -18
UNITS A A mA mA mA mA V
26 1.7
0.46 (VDD/2) +0.1 V pF
(VDD/2) -0.1 VI = GND or VDD
1.25 2
Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=1 DDR/DDR_SDRAM Outputs = 2.5V, TA = 0 - 85C (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2.3 2.5 2.7 VDD3.3_2.5 Power Supply Voltage VDD2.5 2.3 2.5 2.7 Input High Voltage VIH SEL_DDR, PD# input 2.0 Input Low Voltage VIL SEL_DDR, PD# input 0.8 Input voltage level VIN VDD
1
UNITS V V V V
Guaranteed by design, not 100% tested in production.
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ICS93718
Switching Characteristics
DDR_Mode (SEL_DDR = 1), VDD = 2.55%
PARAMETER Operating Frequency Input clock duty cycle Output to Output Skew Duty cycle Rise Time, Fall Time (DDR Outputs)
SYMBOL dtin Tskew DC2 trd, tfd
CONDITION
MIN 66 40 48 47 500
Output crossover skew DDR[0:11] 66MHz to 100MHz, w/loads 101MHz to 167MHz, w/loads Measured between 20% and 80% output, w/loads
TYP 133 50 80 49 50 600
MAX 200 60 100 52 53 700
UNITS MHz % ps % % ps
Switching Characteristics
SD_Mode (SEL_DDR = 0), VDD = 3.35%
PARAMETER Operating Frequency Input clock duty cycle Output to Output Skew Duty cycle Rise Time, Fall Time (SDRAM Outputs) SDRAM Buffer LH Prop. Delay 1 SDRAM Bufer HL Prop. Delay 1
SYMBOL dtin Tskew DC2 trs, tfs tPLH tPHL
CONDITION
MIN 66 40
V T = 1.50V 66MHz to 200MHz V OL = 0.4V, VOH = 2.4V, w/loads Input edge greater than 1V/ns Input edge greater than 1V/ns 0.5
TYP 133 50 150 54 1.5 2 1.9
MAX 200 60
UNITS MHz % ps % ns ns ns
1.7 2.5 2.5
Notes: 1. Refers to transition on non-inverting output. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=t2/t1, were the cycle (t1) decreases as the frequency goes up.
Switching Waveforms
Duty Cycle Timing
t1 t2
1.5V 1.5V 1.5V
SDRAM Buffer LH and HL Propagation Delay
1.5V INPUT 1.5V
1.5V OUTPUT
1.5V
t6
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t7
6
ICS93718
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controlle r (Host) Start Bit Address D2(H ) Dummy Command Code A CK Dummy Byte Count A CK Byte 0 A CK Byte 1 A CK Byte 2 A CK Byte 3 A CK Byte 4 A CK Byte 5 A CK Byte 6 A CK Byte 7 A CK Stop Bit ICS (Sla ve/Re ceiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controlle r (Host) Start Bit Address D3(H ) ICS (Slave/Rece ive r)
A CK
ACK
A CK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS93718
300 mil SSOP
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1 b c D E E1 e h L N VARIATIONS N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
-Ce
b SEATING PLANE .10 (.004) C
48
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP
Ordering Information
ICS93718yFLFT
Example:
ICS XXXX y F LF - T
Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS93718
Revision History
Rev. E Issue Date Description 2/16/2005 Added Lead Free Ordering Information Page # 8
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